In modern computer systems, a processor executes instructions on various data. Both the instructions and data can be obtained from a system memory. To access the system memory, a physical address is used. However, software does not directly provide physical addresses for the processor to use. Instead, hardware of the processor is used to translate a linear address received from the software into a physical address.
In certain processors, there can be processor-based structures to store frequently used or recently used translations to reduce latency. However, it is inevitable that there are so-called misses in which a translation between a requested linear address and a corresponding physical address is not present in the processor. Accordingly, a page walk process is performed to system management to obtain a translation to thus provide an appropriate physical address. While such mechanisms exist, the page walk process can be relatively time consuming, thus increasing latency of memory accesses.